Efficient Pattern Matching in Python

Pattern matching is a powerful tool for symbolic computations. Applications include term rewriting systems, as well as the manipulation of symbolic expressions, abstract syntax trees, and XML and JSON data. It also allows for an intuitive description of algorithms in the form of rewrite rules. We present the open source Python module MatchPy, which offers functionality and expressiveness similar to the pattern matching in Mathematica. In particular, it includes syntactic pattern matching, as well as matching for commutative and/or associative functions, sequence variables, and matching with constraints. MatchPy uses new and improved algorithms to efficiently find matches for large pattern sets by exploiting similarities between patterns. The performance of MatchPy is investigated on several real-world problems

The Pi-puck Ecosystem : Hardware and Software Support for the e-puck and e-puck2

This paper presents a hardware revision of the Pi-puck extension board that now includes support for the e-puck2. This Raspberry Pi interface for the e-puck robot provides a feature-rich experimentation platform suitable for multi-robot and swarm robotics research. We also present a new expansion board that features a 9-DOF IMU and XBee interface for increased functionality. We detail the revised Pi-puck hardware and software ecosystem, including ROS support that now allows mobile robotics algorithms and utilities developed by the ROS community to be leveraged by swarm robotics researchers. We also present the results of an illustrative multi-robot mapping experiment using new long-range Time-of-Flight distance sensor modules, to demonstrate the ease-of use and efficacy of this new Pi-puck ecosystem

Modern architectures for embedded reconfigurable systems - a survey.

Reconfigurable systems, exploiting a mixture of the traditional CPU-centric instruction-stream-based processing with the decentralized parallel application-specific data-dominated processing, provide a drastically higher performance and lower power consumption than the traditional CPU-centric systems. They do it at much lower costs and shorter times to market than the not reconfigurable hardware solutions. They also provide the flexibility that is often required for engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, the reconfigurable computing (RC) systems are adequate for a very broad class of applications across different industry sectors. In this paper, the basic definitions, concepts and features of reconfigurable systems are discussed, as well as their role, purposes they serve and applications that can significantly benefit from them. Also, a comparison of the hardwired systems, RC systems and CPU-centric systems is made, and some main concepts of an effective and efficient reconfigurable computing are discussed. Subsequently, the classification of the RC systems is introduced and their various architecture classes are overviewed. This is followed by a discussion of some major drivers and requirements of the recent and future developments in the modern RC system area, and an overview of the recent and future development trends in the RC architectures. The reconfigurable system area is a very promising, but quite a new field. New opportunities have been opened for this field through introduction of the system-on-a-chip technology, and a big progress has been made in the recent years. Many different reconfigurable devices and computers became commercially available. Nevertheless, multiple aspects of the RC systems, their development and their supporting tools still belong to the open research or development topic

Modern architectures for embedded reconfigurable systems - a survey.

Reconfigurable systems, exploiting a mixture of the traditional CPU-centric instruction-stream-based processing with the decentralized parallel application-specific data-dominated processing, provide a drastically higher performance and lower power consumption than the traditional CPU-centric systems. They do it at much lower costs and shorter times to market than the not reconfigurable hardware solutions. They also provide the flexibility that is often required for engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, the reconfigurable computing (RC) systems are adequate for a very broad class of applications across different industry sectors. In this paper, the basic definitions, concepts and features of reconfigurable systems are discussed, as well as their role, purposes they serve and applications that can significantly benefit from them. Also, a comparison of the hardwired systems, RC systems and CPU-centric systems is made, and some main concepts of an effective and efficient reconfigurable computing are discussed. Subsequently, the classification of the RC systems is introduced and their various architecture classes are overviewed. This is followed by a discussion of some major drivers and requirements of the recent and future developments in the modern RC system area, and an overview of the recent and future development trends in the RC architectures. The reconfigurable system area is a very promising, but quite a new field. New opportunities have been opened for this field through introduction of the system-on-a-chip technology, and a big progress has been made in the recent years. Many different reconfigurable devices and computers became commercially available. Nevertheless, multiple aspects of the RC systems, their development and their supporting tools still belong to the open research or development topic

Modern development methods and tools for embedded reconfigurable systems : a survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded

Interactive volume rendering based on ray-casting for multi-core architectures

The Volume Ray-Casting rendering algorithm, often used to produce medical imaging, is a well-known algorithm and the underlying computation can be easily executed in parallel. This is due to the fact that the huge number of rays, used to sample the volumetric data, can be processed independently. However, the algorithm’s performance may drop substantially when the complexity/size of the volumetric dataset increases. In this paper, we present three implementations of our parallel volume ray-casting algorithm in different multi-core architectures, such as CMPs, GPUs and MPSoCs. Furthermore, we show that using multi-GPUs, that perform in parallel, we can almost halve the rendering time. The performance and aspects of the three implementations are discussed

Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs

The ray tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of 30 frames per second. Therefore, current implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Nonetheless, the algorithm allows for massive parallelization of its computations, which is a strong reason of further improvements. Also, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene that exploits an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture, both running different 3-D scenes. The performance of both implementations are reported and compared. Furthermore, a second GPU has been included in the GPGPU-based implementation, running the same parallel architecture. Thus, primary rays are split among both GPUs for parallel execution and their performance are also presented and compared